The long and complicated process of creating integrated circuits on a silicon wafer involves many performance tests at each manufacturing step. Performance tests are carried out to ensure the quality of manufactured circuits. One challenge of performance testing is balancing the cost of testing with quality. For example, performing a quality test on each and every die (e.g., chip) on a wafer may be costly and time consuming, but the tests may guarantee high chip quality. In the alternative, a tester may limit the number of tests performed to reduce costs; however, by failing to test each and every die on a wafer, there is a risk of overlooking defective chips.
Under conventional techniques, one way of minimizing the number of costly performance tests is to test a sample of chips on a wafer and run more extensive tests only if the initial tests indicate that a problem exists. This technique is used in in-line metrology tests, such as level-to-level overlay alignment tests. In overlay alignment tests, it is sufficient to identify one chip on a wafer that is not aligned properly in order to conclude a failure of the entire wafer. However, since the status (e.g., pass or fail) of a wafer is based on a limited sample of tested chips, a failing wafer may be overlooked when the wafer contains defective chips, but those defective chips fall outside the sample of tested chips. Currently, sample testing does not accurately reflect the quality of an entire wafer.